1. Field of the Invention
This invention relates to methods for fabricating integrated circuits on and in flexible membranes, and to structures fabricated using such methods.
2. Description of Related Art
Mechanically and thermally durable free standing dielectric and semiconductor membranes have been disclosed with thicknesses of less than 2 μm. (See commonly invented U.S. Pat. No. 4,924,589, and U.S. patent application Ser. No. 07/482,135, filed Feb. 16, 1990, now U.S. Pat. No. 5,103,557, both incorporated herein by reference). This disclosure combines the novel use of these technologies and other integrated circuit (IC) processing techniques to form ICs as membranes typically less than 8 μm thick. This approach to IC fabrication falls under the generic industry-established title known as Dielectric Isolation (DI), and is inclusive of subject areas such as Silicon-on-Insulator (SOI) and silicon-on-Sapphire (SOS). ICs formed from dielectric and semiconductor membranes can reduce significantly the number and complexity of processing steps presently used to provide complete IC device isolation; dielectric isolation techniques that provide dielectric isolation on all surfaces of the individual circuit devices comprising the complete IC are not as yet widely used in volume IC fabrication. Integrated Circuits are defined as commonly understood today when referring to SSI, MSI, LSI, VLSI, ULSI, etc. levels of circuit complexity.